JPS6155250B2 - - Google Patents

Info

Publication number
JPS6155250B2
JPS6155250B2 JP13959080A JP13959080A JPS6155250B2 JP S6155250 B2 JPS6155250 B2 JP S6155250B2 JP 13959080 A JP13959080 A JP 13959080A JP 13959080 A JP13959080 A JP 13959080A JP S6155250 B2 JPS6155250 B2 JP S6155250B2
Authority
JP
Japan
Prior art keywords
layer
silicon
region
semiconductor substrate
main surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP13959080A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5763841A (en
Inventor
Kenichiro Ryono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP13959080A priority Critical patent/JPS5763841A/ja
Publication of JPS5763841A publication Critical patent/JPS5763841A/ja
Publication of JPS6155250B2 publication Critical patent/JPS6155250B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76267—Vertical isolation by silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76281—Lateral isolation by selective oxidation of silicon

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
JP13959080A 1980-10-06 1980-10-06 Preparation of semiconductor device Granted JPS5763841A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13959080A JPS5763841A (en) 1980-10-06 1980-10-06 Preparation of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13959080A JPS5763841A (en) 1980-10-06 1980-10-06 Preparation of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5763841A JPS5763841A (en) 1982-04-17
JPS6155250B2 true JPS6155250B2 (en]) 1986-11-27

Family

ID=15248804

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13959080A Granted JPS5763841A (en) 1980-10-06 1980-10-06 Preparation of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5763841A (en])

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58199537A (ja) * 1982-05-14 1983-11-19 Matsushita Electric Ind Co Ltd 高抵抗半導体層の製造方法
US4583282A (en) * 1984-09-14 1986-04-22 Motorola, Inc. Process for self-aligned buried layer, field guard, and isolation
JPH0738435B2 (ja) * 1986-06-13 1995-04-26 松下電器産業株式会社 半導体装置の製造方法
KR910009318B1 (ko) * 1987-09-08 1991-11-09 미쓰비시 뎅끼 가부시기가이샤 반도체 장치의 제조 및 고내압 파묻음 절연막 형성방법
US5372952A (en) * 1992-04-03 1994-12-13 National Semiconductor Corporation Method for forming isolated semiconductor structures

Also Published As

Publication number Publication date
JPS5763841A (en) 1982-04-17

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